The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which has a porous low dielectric constant layer formed for insulation between metal lines.
Memory cells are formed to have a stacked structure as the degree of integration of a semiconductor memory device increases and the demand for a semiconductor memory device operating at a high speed increases. In addition, metal lines for electrical connection of the respective cells are also formed to have a multi-layered structure allowing easy design of a wiring system.
Traditionally, a silicon oxide layer has been used as an insulation material for insulation between metal lines. In this regard, as the semiconductor devices are designed for higher integration and higher speed operation, the parasitic capacitance between metal lines has increased, and the silicon oxide layer has served as a factor for retarding the increase of the driving speed. With this in mind, in the recent semiconductor manufacturing processes, a porous low dielectric constant layer having a low dielectric constant (low k value) no greater than 2.5 has been used as an insulation material for insulation between metal lines. Due to the fact that a dielectric constant k decreases as the size of a pore increases, the porous low dielectric constant layer reduces parasitic capacitance between metal lines, and therefore, increases the operating speed of a semiconductor device.
Hereinbelow, a conventional method for manufacturing a semiconductor device having a porous low dielectric constant layer formed for insulation between metal lines will be described with reference to FIG. 1.
Referring to FIG. 1, an insulation layer 110 and a lower metal line 120 are formed on a semiconductor substrate 100. A porous low dielectric constant layer 130 is formed on the insulation layer 110 including the lower metal line 120 as an interlayer insulation material. By etching the porous low dielectric constant layer 130, a trench is defined for forming an upper metal line, which includes a via-hole for exposing the lower metal line 120. A diffusion barrier 140 is formed on the porous low dielectric constant layer 130 including the surfaces of the via-hole and the trench. A metal layer for a metal line, such as a copper layer, is deposited on the diffusion barrier 140 to fill the via-hole and the trench. An upper metal line 50, which comes into contact with the lower metal line 120, is formed by CMPing (chemically and mechanically polishing) the copper layer and the diffusion barrier 140 to expose the porous low dielectric constant layer 130.
However, since the conventional porous low dielectric constant layer 130 has a low Young's modulus, voids V are likely to be generated and grow therein while subsequent processes are implemented, as shown in FIG. 1. Due to the presence of the voids V, defects can be caused in a semiconductor device.
In detail, it is the norm that annealing is implemented before conducting a CMPing process for the copper layer. During annealing, the semiconductor substrate 100 receives a thermal stress. The thermal stress applied to the semiconductor substrate 100 can result in the deformation of the porous low dielectric constant layer 130 while subsequent processes are implemented. As a consequence, the voids V are likely to be generated in the porous low dielectric constant layer 130.
The voids V, which are generated due to the thermal stress, can serve as a factor for decreasing the hardness of the porous low dielectric constant layer 130. The voids V continuously grow while subsequent semiconductor manufacturing processes and testing processes are implemented so that cracks can occur in the metal lines. Therefore defects can be caused in a semiconductor device and the manufacturing yield can decrease.
The defects resulting from the presence of the voids V can be caused in the same manner in the case where an aluminum layer is used as the material for the metal lines.